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Testing Electrochemical Capacitors: Part 3 – Electrochemical Impedance Spectroscopy


Part 1 - "CV, EIS and Leakage Current" - of this series of notes discusses basic theory of capacitors and describes several techniques to investigate electrochemical capacitors. Part 2 - "Cycle Charge/Discharge and Stacks" - explains Gamry’s Electrochemical Energy software for cycling of energy-storage devices. Effects of different parameters during cycling of single cells and stacks are described. This application note is the third part of notes describing electrochemical techniques for energy-storage devices. This note discusses basics of Electrochemical Impedance Spectroscopy (EIS) and introduces Gamry’s EIS techniques by measurements on single electrochemical capacitors (ECs) and stacks.

All parts of this note can be found in the Application Notes section of Gamry’s website,


Measurements were done on 3 F electric double-layer capacitors (EDLCs) (part # ESHSR‑0003C0‑002R7) and 5 F EDLCs (part # ESHSR‑0005C0‑002R7) from Nesscap1, a 650 F EDLC (part # BCAP0650 P270) from Maxwell2, and a 1 F PAS pseudocapacitor (part # PAS0815LR2R3105) from Taiyo Yuden3. The acronym PAS stands for polyacenic semiconductor, which is a conductive polymer deposited on the electrodes.

The data in this note were recorded using Gamry’s Electrochemical Impedance 300 software and a Reference 3000. All plots were generated and evaluated using Gamry’s software.

Electrochemical Impedance Spectroscopy

EIS is a widely used technique to investigate electrochemical systems. The advantage of EIS is that it is generally non‑destructive to the investigated system. This enables the possibility for further electrochemical measurements and post‑mortem investigations.

EIS is the most common method for measuring the equivalent series resistance (ESR) of ECs. It also allows creating models to describe underlying reaction mechanisms. With these models capacitor non‑idealities can be investigated.

Generally, a sinusoidal AC excitation signal is applied to the investigated system during an EIS experiment, and the AC response is measured. The frequency of the input signal varies during the measurement. Finally, the impedance Z of the system is calculated, expressed in terms of magnitude Z0 in Ω and phase-shift ø in degrees.

App Note Basics of EIS
If you need basic information on EIS, see Gamry's application note: Basics of Electrochemical Impedance Spectroscopy

EIS Measurement Modes

Gamry’s software can measure impedance spectra using four different modes:

  • Potentiostatic
  • Galvanostatic
  • Hybrid
  • OptiEIS

In potentiostatic mode, a DC voltage is applied that is superimposed by an AC voltage signal. The frequency of the signal is changed during the experiment and the phase-sensitive AC current response is measured.

Galvanostatic mode is similar to potentiostatic mode. In contrast, a DC current superimposed by an AC current signal is applied to the system, and the phase-sensitive AC voltage response is measured.

Hybrid EIS also uses galvanostatic cell control. In addition, the amplitude of the AC current is adjusted to maintain a nearly constant AC potential response.

Potentiostatic mode is most common in research. However, small errors in the applied DC voltage can lead to huge DC currents in low‑impedance cells, thus destroying the cell. Therefore galvanostatic and Hybrid EIS are preferred for low-impedance cells.

Three application notes give suggestions for making low-impedance EIS measurements.

OptiEIS is a multisine technique and differs from the other methods described above. Instead of a single sinusoidal waveform with only one frequency, multiple waveforms with several frequencies are applied to the system simultaneously. Hence the time for EIS measurements can be reduced by up to a factor of four. OptiEIS can be run potentiostatically or galvanostatically.

For more information on Multisine EIS see application note: OptiEIS: A Multisine Implementation

Randles Model for Electrochemical Capacitors

The ideal capacitor does not exist: in reality, several effects lead to imperfections in the system. Hence, different models are used to describe the investigated system. The most common and simplest model fitted to EIS spectra of electrochemical capacitors is a simplified Randles model, shown in Figure 1:

Diagram of a simplified Randle’s model

Figure 1. Diagram of a simplified Randle’s model.

The circuit elements in the model are:

  • ESR         Equivalent series resistance
  • Rleakage   Leakage resistance
  • C            Ideal capacitance

Resistances from the electrolyte, the electrodes, and electrical contacts are summed in the ESR. A small ESR leads to better performances of energy-storage devices.

In contrast, a small leakage resistance Rleakage leads to a higher leakage current, which is responsible for self-discharge of a charged capacitor when no external load is connected. The leakage resistance is modeled parallel to C.

Figure 2 shows a Bode plot of a Randles model in the frequency range between 10 kHz and 1 µHz. The fit‑parameters are typical values for electrochemical capacitors:

  • ESR 100 mΩ
  • Rleakage 100 kΩ
  • C     1 F

 Bode plot of Randle’s model. (circle) magnitude, (cross) phase

Figure 2. Bode plot of Randle’s model. (circle) magnitude, (cross) phase.

The Bode spectrum of a typical Randles model has three regions:

  • Above 10 Hz, magnitude and phase approach 100 mΩ and 0° respectively. The ESR dominates this region.
  • Between 100 µHz and 100 mHz, capacitance controls the impedance. Magnitude versus frequency is linear (on the log-log Bode plot) with a slope of  -1 and the phase approaches  -90˚.
  • Below 10 µHz, the impedance begins a transition back towards resistive behavior as leakage resistance becomes dominant. This transition is incomplete even at 1 µHz.

EIS spectra of real devices rarely give much information about leakage resistance because its effects are seen at impractically low frequencies. Measurements at these frequencies take a long time.

Part 1 of this application note series describes in detail methods to measure leakage current.

Transmission-line Models for Electrochemical Capacitors

Real electrochemical capacitors do not show the simple behavior of a Randles model. Figure 3 shows a Bode plot of a 3 F EDLC. In addition, two different models are shown: the simplified Randles model (red curve) and the Bisquert Open model (green curve).

The impedance of the 3 F EDLCs used to generate data for this note is high enough that any control mode can be used. Because potentiostatic EIS is most common, this mode was used.

The capacitor was first charged to 2.7 V and held at this potential for 10 min. For the EIS experiment, DC voltage was set to 2.7 V superimposed by an AC voltage of 1 mV. The frequency ranged from 10 kHz to 100 µHz.

Bode diagram of a potentiostatic EIS test on a 3 F EDLC (blue). (red) Randle’s model, (green) Bisquert open model. (purple) magnitude, (+) phase.

Figure 3. Bode diagram of a potentiostatic EIS test on a 3 F EDLC (blue). (red) Randles model, (green) Bisquert open model. (purple) magnitude, (+) phase.

As expected, fitting Randles model to the spectrum shows poor agreement. The fit results are:

  • ESR         45.5 mΩ ± 0.2 mΩ
  • Rleakage   3.6 kΩ ± 0.4 kΩ
  • C            2.75 F ± 0.01 F

This result is typical for EIS spectra of electrochemical capacitors in which electrode porosity leads to very non‑uniform access of the electrolyte to the electrode surface, and Faradaic reactions occur. Simple resistor and capacitor models do not apply.

Differences between Randles model and real ECs include:

  • Between 10 Hz and 10 kHz, magnitude is not constant but slightly increasing. The transition from resistive to capacitive behavior occurs in stages.
  • Phase never approaches the simple model’s 0˚ prediction at higher frequencies.
  • No sign of leakage resistance is seen in this frequency range.

The fit to the data is much better using a porous-electrode transmission-line model. Figure 4 shows the Bisquert Open model that describes also electrode porosity.

Diagram of the Bisquert open model.

Figure 4. Diagram of the Bisquert open model.

Among ESR, a pore resistance Rm is added that increases with increasing pore depth. A constant-phase element (CPE) replaces the ideal capacitance and defines inhomogeneities of the electrode surface in ECs. An interfacial resistance Rk similar to the leakage resistance is parallel to CPE and completes the model.

For more information on transmission line models, see application note:Demystifying Transmission Lines:  What are They, Why Are They Useful?

The fit of the Bisquert open model in Figure 3 is represented in green. The fit-parameters are

  • ESR          38.2 mΩ ± 0.4 mΩ
  • Rm           96 mΩ ± 17 mΩ
  • Rk           1.3∙1034 Ω ± 1∙1038 Ω
  • Ym (CPE) 2.54 S∙sα ± 0.15 S∙sα
  • α (CPE)   0.97 ± 0.03

The Bisquert Open model complies much better with the Bode plot in Figure 3 than the Randles model, and it overlaps nearly perfectly.

Transmission-line models take into account the stepwise increase of the magnitude at higher frequencies. The transition region from resistive to capacitive behavior at frequencies above 100 mHz is described much better.  Hence the fit-value for the ESR is smaller than the result of the Randles model.

The high uncertainty in the interfacial resistance Rk is expected. This resistance dominates the impedance in the low-frequency region that is not included in the spectrum.

EIS on a 3 F EDLC at different potentials

For ideal EDLCs, EIS spectra are independent of the applied DC voltage. However, real devices do not show this tendency.

Figure 5 shows Bode plots of a 3 F EDLC recorded at five different DC potentials: 0 V, 1 V, 2 V, 3 V, and 3.5 V. The last value is much higher than the 2.7 V specification of the EDLC.

The spectra were measured potentiostatically with an AC voltage of 1 mVrms in a frequency range from 10 kHz to 10 mHz. The capacitor was held at the DC voltage for 10 minutes before each measurement.

Bode diagrams of potentiostatic EIS tests on a 3 F EDLC. (blue) 0 V, (green) 1 V, (red) 2 V, (yellow) 3 V, (violet) 3.5 V. (black) magnitude, (+) phase.

Figure 5. Bode diagrams of potentiostatic EIS tests on a 3 F EDLC. (blue) 0 V, (green) 1 V, (red) 2 V, (yellow) 3 V, (violet) 3.5 V. (black) magnitude, (+) phase.

Obviously, this EDLC shows non-ideality between 1 Hz and 10 kHz. Exceeding the rated voltage of the capacitor can cause decomposition and deposition reactions on the electrode surface. These irreversible Faradaic reactions can lead to an increase in ESR shown in the frequency range above 1 Hz where ESR dominates the impedance.

Below 1 Hz, impedance is decreasing with increasing voltage. In this frequency region, impedance depends on the DC voltage, so the capacitance increases and must also depend on DC voltage. Increased capacitances at higher potentials can be at the cost of shorter lifetimes.

EIS on a 1 F pseudocapacitor at different potentials

Just as for ideal EDLCs, EIS spectra recorded on an ideal pseudocapacitor should superimpose at different DC voltages. Yet for real pseudocapacitors this behavior does not apply.

Figure 6 shows Bode plots of a 1 F PAS pseudocapacitor recorded by potentiostatic EIS mode. The DC voltages were 0 V, 1 V, 2 V, and 2.4 V. The AC voltage was set to 1 mVrms. The frequency range was between 10 kHz and 10 mHz.

 Bode diagrams of potentiostatic EIS tests on a 1 F PAS pseudocapacitor. (blue) 0 V, (green) 1 V, (red) 2 V, (yellow) 2.4 V. (black) magnitude, (+) phase. For details, see text

Figure 6. Bode diagrams of potentiostatic EIS tests on a 1 F PAS pseudocapacitor. (blue) 0 V, (green) 1 V, (red) 2 V, (yellow) 2.4 V. (black) magnitude, (+) phase. For details, see text.

Just as for EDLCs, pseudocapacitors show voltage-dependence in impedance at lower frequencies. With increasing voltage, impedance decreases.

In contrast to the 3 F EDLC (Figure 5), this 1 F pseudocapacitor showed no voltage-dependence at frequencies above 10 Hz.

EIS on a Low-ESR 650 F EDLC

EIS measurements on low ESR capacitors are difficult. The technique generally requires:

  • True 4 terminal measurements
  • Galvanostatic cell control
  • Low-resistance contacts
  • Twisted-pair or coaxial cell leads

Figure 7 shows the connections used to record the EIS spectrum of a 650 F EDLC. 1.5 mm thick copper sheets were used for the connections. The current-carrying leads (green and red) and the voltage sensing leads (white and blue) are on opposite sides of the device.

warning supercap3  Warning: Avoid shorting capacitor terminals though low-resistance connections. Very dangerous currents of hundreds or even thousands of ampères could flow.

As mentioned above, galvanostatic mode is necessary for low-impedance cells. Using potentiostatic mode, small errors in DC voltage can lead to high currents destroying the cell or exceeding the potentiostat’s specifications.

Electrode connections for measurements on a 650 F EDLC. Working (green), Counter (red), Working sense (blue), and Reference (white).

Figure 7. Electrode connections for measurements on a 650 F EDLC. Working (green), Counter (red), Working sense (blue), and Reference (white).

Figure 8 shows a Hybrid EIS spectrum of a 650 F EDLC. The capacitor was first charged to 2 V and held at this potential for 30 min to maintain a constant voltage during the EIS measurement. The DC current was zero and the AC voltage was 0.1 mVrms. The EIS spectrum was recorded from 1 kHz to 10 mHz.

Note that Hybrid EIS is still working in galvanostatic mode although an AC voltage is defined in the setup. The galvanostat modifies the AC current to maintain nearly the adjusted AC voltage response.

Bode diagram of a Hybrid EIS test on a 650 F EDLC. (blue) magnitude, (+) phase.

Figure 8. Bode diagram of a Hybrid EIS test on a 650 F EDLC. (blue) magnitude, (+) phase.

This 650 F EDLC has a rated ESR of less than 600 µΩ at 1 kHz. The measurement yields a value of 418 µΩ, which is less than this capacitor’s rated ESR of 600 µΩ.

Looking at the DC potential of the EDLC during the EIS measurement, it changes only by about 2 mV, which is necessary for reliable results.

OptiEIS: a Multisine technique

Gamry’s OptiEIS enables the user the possibility to perform EIS measurements faster than with conventional single-sine techniques.

Figure 9 shows Bode plots of a potentiostatic EIS test and an OptiEIS experiment in potentiostatic mode on a 3 F EDLC. The capacitor was first charged to 2.7 V and held at this potential for 20 minutes. A DC voltage of 2.7 V and an AC voltage of 10 mV were applied. The frequency ranged from 40 Hz to 10 mHz.

Bode diagrams of a potentiostatic EIS test (blue) and an OptiEIS test (red) on a 3 F EDLC. (black) magnitude, (+) phase. For details, see text.

Figure 9. Bode diagrams of a potentiostatic EIS test (blue) and an OptiEIS test (red) on a 3 F EDLC. (black) magnitude, (+) phase. For details, see text.

Both Bode plots of the potentiostatic EIS and OptiEIS experiments overlap perfectly. In low-noise mode, the potentiostatic EIS test takes about 30 min. With OptiEIS, measurement time is reduced to only 9 min, which is a factor of about three in reduction.

EIS during Cycling Experiments

EIS can be combined with other techniques, such as cyclic charge-discharge (CCD) tests. This combination enables investigation of changes in a system with time. For detailed information about practical applications and evaluation of CCD tests see Part 2 of this application note series.

CCD test on a 3 F EDLC over 50,000 cycles interrupted by galvanostatic EIS experiments. For details, see text.

Figure 10. CCD test on a 3 F EDLC over 50,000 cycles interrupted by galvanostatic EIS experiments. For details, see text.

Figure 10 shows the changes of capacity during a CCD experiment. Ten sequences were run; each had 5000 cycles. Prior to the first cycle, and after each sequence, a galvanostatic EIS experiment was performed. The total number of cycles was 50 000.

To perform complex sequences, Gamry offers the Sequence Wizard It allows building of individual sequences with a wide spectrum of techniques.

For the CCD test, a 3 F EDLC was first charged to 1.35 V and then cycled between 1.35 V and 3.5 V with a current of ±2.25 A.

Capacity decreases with increasing cycle number. Because the upper voltage limit of 3.5 V is way above the limitations of the EDLC, irreversible reactions on the electrode surface can occur, which decrease the performance.

Capacity decreases with increasing cycle number

Figure 11. Bode diagrams of galvanostatic EIS tests on a 3 F EDLC during cycling. (blue) 1st cycle, (green) 10,000th cycle, (red) 20,000th cycle, (yellow) 30,000th cycle, (magenta) 40,000th cycle, (cyan) 50,000th cycle. (black) magnitude, (+) phase. For details, see text.

Figure 11 shows the Bode plots. Zero DC current and 10 mArms AC current were applied. The spectra were recorded from 10 kHz to 100 mHz. Prior to each EIS test, the potential was held at 3.5 V for four hours.

Note: The hold step is necessary, keeping the system in a steady state during the galvanostatic EIS measurement, to fulfill the stability criterion for EIS.

Impedance increases in the frequency range between 1 Hz and 10 kHz with increasing cycle number. In this region ESR dominates the impedance. Evaluation of the fits for these spectra confirms that the ESR increases. After 50 000 cycles the ESR increased by about 14 mΩ, an increase of more than 30 %.

In contrast, capacitance decreases with increasing cycle number caused by irreversible reactions that can occur on the electrode surface.

Table 1 lists the fit values for the ESR and capacitance, dependent on the cycle number.

Cycle #







ESR [mΩ]







C [F]







Table 1. Change in ESR and capacitance versus cycle number.

EIS on Stacks

Single energy-storage devices are stacked together for high‑voltage applications. For this, cells are connected in serial and parallel circuits. For further information about cell stacks see Part 2 of this application note series.

Figure 12 shows a test setup for stack measurements used in this note. It consists of a serial connection of two 3 F EDLCs and one 5 F EDLC. A higher ESR is simulated for the second capacitor with a 0.5 Ω resistor in series. The voltage of each single cell was measured with individual channels of Gamry’s Auxiliary Electrometer.

Serially connected capacitors with Auxiliary Electrometer connections

Figure 12. Serially connected capacitors with Auxiliary Electrometer connections (AECH 1, AECH 2, and AECH 3). Serial resistor R simulates a higher ESR.

For the EIS experiments with a stack, every single cell was initially charged to 1 V. After this, the stack was charged to 9 V with a current of 3 A. The potential was held for 20 minutes prior to the EIS measurement.

Figure 13 shows Bode plots of the stack and all three single cells that were recorded simultaneously with the Auxiliary Electrometer. The EIS experiment was performed in galvanostatic mode with zero DC current and 10 mArms AC current. The frequency ranged from 10 kHz to 1 mHz.

Bode diagrams of a galvanostatic EIS test on a stack of EDLCs.

Figure 13. Bode diagrams of a galvanostatic EIS test on a stack of EDLCs. (blue) stack, (green) C1, (red) C2 + R, (yellow) C3. (black) magnitude, (+) phase.

At frequencies above 1 Hz, differences in ESR of each single cell can be seen. As the total voltage U of the stack, also the total ESR is the sum of the parameters of each single cell. Hence spectra are shifted upwards above 1 Hz with increasing ESR.

In contrast, the total capacitance C of a stack is the inverse of the sum of the reciprocal single capacitances. Hence total C is lower than the single capacitances. Below 100 mHz, in the linear region of the magnitude, spectra are shifted towards the bottom-left corner of the diagram with increasing capacitance.

Table 2 summarizes some parameters of the investigated stack and its single cells. ESR and capacitance C were calculated by fits from each EIS spectrum. The potential V was recorded during the charge step.


U [V]

ESR [mΩ]

C [F]









C2 + R








Table 2. Measured parameters of the stack and its single cells.

Looking only at the parameters of the stack does not reveal imbalances of single cells. For example, if the stack were perfectly balanced and charged to 9 V, all single capacitors would be evenly charged to 3 V.

Because of unbalanced cell parameters (e.g., different ESR and different capacitances), the charge potentials of the single cells vary. You cannot see these differences in the total stack voltage, which is still 9 V.

Because capacitor C2 has the highest simulated ESR, it overcharged by more than 0.5 V, whereas C1 and C3 did not reach the desired potential. Overcharging can damage a cell and drastically reduce performance and lifetime.

By using the Auxiliary Electrometer, the whole stack and each single cell can be investigated simultaneously. In this way, imbalances in capacitances, ESR, and cell potentials can be observed. The stack can be balanced by adjusting these parameters.


This application note discusses theory and practice of EIS measurements with electrochemical capacitors. We showed that EIS is an indispensable tool to investigate energy-storage devices. Two models were explained to fit Bode spectra of ECs. For reliable fitting, transmission-line models are necessary to describe the porosity of high‑surface electrodes used in ECs.

Based on several measurements on ECs, different techniques were described: potentiostatic EIS, galvanostatic EIS, Hybrid EIS, and Gamry’s multisine technique called OptiEIS. To show the wide variety of EIS applications, CCD tests were combined with EIS measurements to monitor changes in the system over time.

Finally, stack measurements were performed using Gamry’s Auxiliary Electrometer. In this way, single cells of a stack can be investigated simultaneously in order to balance individual cell parameters.

1 Nesscap Energy Inc., 24040 Camino Del Avion #A118, Monarch Beach, CA, 92629.

2Maxwell Technologies, Inc., 3888 Calle Fortunada, San Diego, CA, 92123.

3Taiyo Yuden (U.S.A.) Inc., 497 Hooksett Road, PMB # 38, Manchester, NH 03104.