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Testing Electrochemical Capacitors: Part 2 — Cyclic Charge Discharge and Stacks

cyclic charge dischargeIntroduction

This application note is Part of 2 describing electrochemical techniques for energy-storage devices. It explains Gamry’s PWR800 measurement software and describes techniques to investigate electrochemical capacitors. This application note can also be extended to testing batteries.

An introduction to electrochemical capacitors is found in Part 1 for this application note, which discusses techniques familiar to chemists who have worked outside of energy-storage applications. Part 3 describes theory and practice of EIS measurements on capacitors.

You can find all Parts of this application note in the Application Notes section on Gamry’s homepage,


The data shown in this note were recorded on a Gamry Instruments potentiostat using Electrochemical Energy software. Tests were run with commercial 3 F (P/N ESHSR-0003C0-002R7) and 5 F (P/N ESHSR-0005C0-002R7) electric double-layer capacitors (EDLCs) from Nesscap[1]. EDLCs exhibit much lower charge and discharge times than batteries, reducing dramatically the time for measurements.

Basics of Cyclic Charge-Discharge

Cyclic Charge-Discharge (CCD) is the standard technique used to test the performance and cycle-life of EDLCs and batteries. A repetitive loop of charging and discharging is called a cycle.

Most often, charge and discharge are conducted at constant current until a set voltage is reached. The charge (capacity) of each cycle is measured and the capacitance C, in farads (F), is calculated (Eq. 1).

     Most often, charge and discharge are conducted at constant current until a set v

where Q is the charge in coulombs, and V is the voltage window. Both are plotted as a function of cycle number. This curve is called the capacity curve.

In practice, charge is commonly called capacity. Usually, capacity has the unit of ampere-hour (Ah), where 1 Ah = 3600 coulombs.

If capacity falls by a set value (10 % or 20 % is customary), the actual number of cycles indicates the cycle-life of the capacitor. In general, commercial capacitors can be cycled for hundreds of thousands of cycles.

Figure 1 shows CCD data recorded on a new 3 F EDLC. Five cycles are shown with current and voltage plotted versus time, with each cycle graphed in a different color.

The lighter-colored waveform is the current applied to the capacitor. The darker-colored waveform shows the measured voltage. The capacitor was cycled between 0 V and 2.7 V with a current of ±0.225 A.

CCD test on a new 3 F EDLC.

Figure 1. CCD test on a new 3 F EDLC. Voltage and current versus time are shown for five cycles. For details, see text.

This new EDLC shows almost ideal behavior: the slope of the curve (dV/dt) is constant and is defined by Eq. 2.

New EDLC shows almost ideal behavior: the slope of the curve (dV/dt) is constant

V is the cell potential in volts (V), I is the cell current in ampères (A), and Q is the charge in coulombs (C) or ampère-seconds (A·s).

Figure 2 shows the same CCD procedure but on a 3 F capacitor damaged by excessive voltage. This capacitor’s behavior is obviously far from ideal.

CCD test on a damaged 3 F EDLC.

Figure 2. CCD test on a damaged 3 F EDLC. Voltage and current versus time are shown for five cycles. For details, see text.

Increased self-discharge causes an exponential shape of charge and discharge voltage versus time. A higher equivalent series resistance (ESR) also leads to a large voltage drop (IR-drop) at each half-cycle, which dramatically reduces power and capacity. The damage has greatly decreased the efficiency of this EDLC.

Gamrys Cyclic Charge-discharge Software

Figures 1 and 2 showed individual charge and discharge curves. More commonly, CCD data are plotted as a capacity curve: capacity versus cycle number.

Gamry’s CCD data file contains additional information that allows plotting ∆ capacity, energy, energy efficiency, Coulombic efficiency, and capacitance versus cycle number.

Figure 3 shows the typical setup windows for a CCD experiment, presented in three pages. A simple CCD test consists of a repetitive loop through several steps:

  1. Constant current charge

  2. Potentiostatic hold (optional)

  3. Rest at Open-Circuit Potential (OCP) (optional)

  4. Constant-current discharge

  5. Rest at (OCP) (optional)

On Page 1 of the setup, output file name as well as various cell and setup parameters can be defined. The Working Lead parameter specifies how the potentiostat is connected to a cell. When the working lead (green) is connected to the positive electrode (discharge cathode) of the electrochemical cell, select the Positive radio button for this parameter. Otherwise, select the Negative radio button for this parameter.

The optional Cable Check warns in a separate window how cable connections are appropriate for the selected Cell Type.

Gamry's Software Help Files
Please refer to Gamry’s Help menu for a detailed description of all setup parameters.


fig3 1 software setup for a CCD experiment.Figure 3-2. Software setup for a CCD experiment.Figure 3. Software setup for a CCD experiment.

Figure 3. Software setup for a CCD experiment.

The Reference 3000 with an Auxiliary Electrometer allows measuring the voltage of up to eight cells in a serially connected stack individually. If connected, an optional parameter appears in the setup window. This parameter consists of checkboxes to select which channels are active during an experiment.

All relevant parameters for the charge and discharge steps are set on Page 2 of the CCD setup (see Figure 3).

A CCD experiment can be started with a charge or discharge step. The length of a CCD test can be controlled by the cycle number and various Loop End criteria (see Figure 4). The measurement stops after reaching the cycle limit, a loop end criterion, or it may be cancelled at any time by pressing F1‑Abort.

fig4 loop end criteria

Figure 4. Selectable Loop End criteria which can terminate a CCD experiment prematurely.

The individual length of a charge/discharge step can be further controlled by setting a maximum time or various stop criteria (see Figure 5). Stop criteria can be defined by the cell’s voltage, temperature behavior, charge, or energy. A charge/discharge step is terminated prematurely if any of the set criteria is met. The CCD experiment continues then with the next step.

After each single step, the cell’s capacity is automatically calculated and shown in a capacity curve.

Figure 5. Selectable charge/discharge Stop criteria.

Figure 5. Selectable charge/discharge Stop criteria.

The discharge step allows four different modes: Constant Current, Constant Power,Constant Load, or ConstantC‑rate (Capacity * N, Capacity / N) (see Figure 6). Please note that the charge step can be only performed in Constant Current mode for CCD experiments. However, single charge experiments can be also performed in Constant C-rate mode.

Selectable modes for the discharge step (Constant C rate mode is shown

Figure 6. Selectable modes for the discharge step (Constant C‑rate mode is shown).

The C‑rate (charge or discharge rate) defines how fast a battery is charged or discharged. In general, the capacity of a battery is rated at 1C. This means that a battery with a capacity of 1 Ah provides a current of 1 A for one hour. Higher C‑rates provide larger current but for a shorter period.

Two parameters are crucial when selecting Constant C‑rate mode. The first parameter is the rated/expected capacity of the battery and is set in the first setup window of a CCD experiment. The second parameter is the multiplier/divisor N and defines the rate. Note that N is an integer. Use Capacity * N for C-rates above 1C and Capacity / N below 1C.

Enabling Voltage Finish holds the cell potentiostatically at the end potential until the measured current falls below a limiting value or a set time is reached. This step is especially advisable if (optional) EIS experiments are performed as it ensures that the potential remains stable and does not drift.

The corresponding EIS parameters can be set on Page 3 of the CCD setup. In addition, the save intervals for raw data (individual charge and discharge curves) as well as impedance data can be selected.

CCD on Single 3 F EDLCs

Different voltage limits

fig7 percentage change capacity

Figure 7. Percentage change of capacity of a 3 F EDLC during cycling to different voltage limits. (blue) 2.7 V, (green) 3.1 V, (red) 3.5 V, (violet) 4.0 V. For details, see text.

Cycle-life depends on a number of variables:

  • Limiting voltage,
  • Current used for charge and discharge,
  • Temperature

To demonstrate the first point, four 3 F EDLCs were cycled to different voltage limits, most of them well beyond the 2.7 V maximum voltage specified for the EDLC.

Figure 7 shows the corresponding curves with the relative change of capacity for up to 50 000 cycles. The capacitors were charged and discharged with a current of ±2.25 A. The lower voltage limit was 1.35 V, which is the half-rated voltage of the EDLC. The upper voltage limits were set to 2.7 V, 3.1 V, 3.5 V, and 4.0 V.

Capacity-fade is more pronounced on the samples charged to higher voltage limits. The capacity is reduced by only 10% after 50 000 cycles at potentials below 3.0 V. The capacitor charged to 4.0 V lost 20% of its capacity after 500 cycles.

The strong degradation in performance at higher potentials mainly occurs when Faradaic electrochemical reactions decompose the electrolyte. This can inhibit the electrode surface, lead to gas formation, damage the electrodes, and have other adverse effects.

Different charge and discharge-currents

Cycle-life also depends on the applied current. To demonstrate the effect of higher currents on CCD experiments, current values significantly beyond the specifications of the capacitor were chosen. The used 3 F capacitors used are specified for currents of 3.3 A.

For these experiments currents larger than 3 A were needed. This requires the use of a Gamry Instruments Reference 30k Booster.

The Reference 30k Booster is an extension for the Reference 3000, with a compliance current expanded to ±30 A. It works with all applications for the Reference 3000, including the Auxiliary Electrometer. For more information, visit Gamry’s website:

Three capacity plots with different charge and discharge currents are shown in Figure 8. The EDLCs were charged and discharged between 1.35 V and 3.5 V. The applied current was set to 2.25 A, 7.5 A, and 15 A.

Capacity curves of a 3 F EDLC during cycling with different currents.

Figure 8. Capacity curves of a 3 F EDLC during cycling with different currents. (blue) 2.25 A, (green) 7.5 A, (red) 15 A. 

The capacity curves at higher currents show a steep capacity decline with increasing cycle number. The two EDLCs that were cycled with 7.5 A and 15 A failed before reaching 400 and 800 cycles respectively.

Even on the first CCD cycle, higher currents lead to reduced capacity. Voltage is lost due to IR-drop (VLoss) according to Eq. 3:

higher currents lead to reduced capacity

The IR-drop voltage is not useful in charging and discharging the capacitor. Both charge and discharge have their effective voltage range Veff reduced by twice the IR-drop voltage.

Assuming 40 mΩ ESR for 3 F capacitors, we expect these parameters for different currents:

I (A)



Q (mAh)

PLoss (W)
















Table 1. Estimated IR-drop voltage, effective voltage range, capacity, and power loss for 3 F EDLCs with 40 mΩESR. For details, see text.

The IR-drop reduces capacity by about 19% and 50% respectively. Note the rough agreement between the initial capacities of the measurements with 7.5 A and 15 A in Figure 8 and Table 1.

The two capacitors cycled with 7.5 A and 15 A got quite hot before they failed.

The heat generated by rapid cycling is also caused by IR-losses. Assuming a constant ESR, the power loss PLoss in these devices can be estimated from Eq. 4:

The heat generated by rapid cycling is also caused by IR-losses.


Table 1 shows that power loss is estimated to be greater than 2 W, even at 7.5 A. The small 3 F capacitors used for these tests cannot dissipate this much power without getting very hot. Heat can cause degradation of the electrolyte and dramatically reduce lifetime.

The capacitor cycled at 15 A was so badly swollen at the end of the test that it was surprising it had not burst.

CCD on Stacks for Higher Voltages

Balanced stack

For high-power applications, several energy-storage devices are often combined in serial and parallel circuits. For serially-connected capacitors, Eqs. 5 and 6 apply:

serially-connected capacitors

The total capacity for n identical capacitors is the nth fraction of the capacity of a single capacitor. The individual voltages of the capacitors are summed to give the total voltage of the stack.

Figure 9 shows a schematic diagram for a serially connected stack of capacitors.

stack of capacitors

Figure 9. Diagram of serially-connected capacitors with Auxiliary Electrometer connections.

If all single cells in a stack show the same parameters, the stack is called balanced. The stack is unbalanced if there are cells that differ in performance parameters like capacitance, ESR, or leakage resistance.

Gamry’s Auxiliary Electrometer (AE) enables detailed investigation of single cells in a stack. Each individual channel (AECH 1, AECH 2, AECH 3,…) measures the voltage across a cell.

Capacity curves cannot show irregularities in stacks. All cells receive the same current so their capacities are identical. In the following sections, tests were done with small stacks containing three series-connected EDLCs. The stacks were deliberately unbalanced to show the effect of two common irregularities. To reveal these irregularities, different plots were used.

Unbalanced stack with different capacitances

Using capacitors with different capacitances in a stack leads to fluctuations in voltage defined by Equation 7.

Using capacitors with different capacitances

Applying a constant charge Q on a stack leads to a lower voltage Vi for single cells with higher capacitance Ci.

A serial stack made up of two 3 F EDLCs (C1, C2) and one 5 F EDLC (C3) (see also Figure 9) was used to test an unbalanced stack. All three capacitors were initially charged to 1.35 V before being added to the stack, so the initial stack voltage was close to 4 V.

The stack was cycled for 500 cycles with a current of ±0.225 A. The test started with a charge step. The cycle limits were set to 4 V and 9.5 V. The voltage of each single cell was measured with three AE channels.

Limiting potentials for the charge (darker) and discharge process (lighter) of a

Figure 10. Limiting potentials for the charge (darker) and discharge process (lighter) of an unbalanced stack with two 3 F EDLCs (blue C1, green C2) and one 5 F EDLC (red C3). 

Figure 10 shows one presentation of the data from this test. The limiting voltages of each channel for the charge (darker colored) and discharge step (lighter colored) versus cycle number are plotted.

As expected, the final discharge voltage for each cell (regardless of capacitance) is close to 1.3 V. The small deviations from 1.3 V are probably caused by leakage-current imbalance, described later.

The final charge voltage is more interesting. If we had a balanced stack, the fully charged stack voltage of 9.5 V would be evenly divided among the cells so each cell would charge to about 3.16 V.

The 3 F EDLCs (C1 and C2) are charged to about 3.36 V in the unbalanced stack. Each is overcharged by about 200 mV. The 5 F capacitor (C3) is only charged to about 2.7 V and therefore undercharged by 400 mV. The voltage imbalance is independent of the cycle number.

Figure 11 shows the calculated energy of the charge step versus cycle number for the same measurement.

Charge energy versus cycle number of single cells in an unbalanced st

Figure 11. Charge energy versus cycle number of single cells in an unbalanced stack with two 3 F EDLCs (blue C1, green C2) and one 5 F EDLC (red C3).

In a capacitor stack with unbalanced capacitor values, the capacitors with the highest capacitances have a lower effective voltage range. These deviations in voltage also lead to differences in energy.

The energy of the 5 F EDLC is reduced due to lower voltage limits. The two 3 F EDLCs try to balance this voltage loss with higher voltages. Their energy content increased.

In extreme cases, the voltage (and energy) increase can be large enough to damage the cells causing a safety hazard.

Unbalanced stack with different leakage resistances

Leakage resistance affects both stack performance and cycle-life. It can change as a capacitor ages. Low leakage resistances lead to higher leakage currents which discharge the cell without external current applied.

Leakage resistance can be modeled as a resistor parallel to a capacitor (see Figure 12).

self-discharge from leakage current

Figure 12. Diagram of serially-connected capacitors with AE connections. Parallel resistors R1 and R2 simulate different leakage resistances.

Figure 13 shows the self-discharge from leakage current. Two resistors (R1 = 16.5 kΩ, R2 = 154 kΩ) were installed parallel to C1 and C2. The intrinsic leakage resistance for C3 is in the MΩ-range. All three capacitors have a nominal capacitance of 3 F. The stack was charged to 8.1 V using a charge current of 0.225 A. After charging to 8.1 V the voltage was recorded in currentless state for 6 h.

Internal leakage current leads to a continuous voltage drift that discharges the cell. Capacitor C1 with the lowest leakage resistance has the highest leakage current. It causes the highest loss in voltage (about 850 mV). In comparison, the total voltage-loss of the stack is about 1 V after 6 h.

Self discharge over 6 hours of an unbalanced stack

Figure 13. Self‑discharge over 6 hours of an unbalanced stack  (violet) and its single cells (blue C1, green C2, red C3) with different leakage resistances.

The calculated leakage current for C1 is 47 µA whereas the other two capacitors exhibit values of only 7 µA (C2) and 2 µA (C3).

This measurement was done with a special self-discharge script in the software (Revision 5.61 and newer) named PWR Self-Discharge.exp

Higher leakage currents also lead to increased loss in energy and power. Figure 14 shows the behavior of energy during cycling. The prior stack setup was cycled for 500 cycles between 4 V and 8.1 V with a current of ±0.225 A.

Charge energy versus cycle number of single cells

Figure 14. Charge energy versus cycle number of single cells  (blue C1, green C2, red C3) with different leakage resistances in an unbalanced stack.

Higher leakage currents cause continuous energy-fade during cycling. The energy of C1 decreases continuously caused by higher self-discharge. This is in contrast to Figure 10 and Figure 11, where voltage- and energy-imbalances were independent of the cycle number.

Capacitors C2 and C3 compensate for this loss and overcharge to higher voltages. Energy increases but this may be at the cost of lower electrochemical stability and decreased cycle-life.


This application note describes Gamry’s CCD software by tests on single 3 F EDLCs and small stacks. Effects of different setup parameters on performance of EDLCs were presented and the influence of common irregularities in stacks was described. The combination of single-cell investigation and recording of multiple parameters enables accurate evaluation of irregularities in stacks.

[1]Nesscap Energy Inc., 24040 Camino Del Avion #A118, Monarch Beach, CA 92629.